devela::_dep::raw_cpuid

Struct ThermalPowerInfo

pub struct ThermalPowerInfo { /* private fields */ }
Available on crate feature dep_raw_cpuid only.
Expand description

Query information about thermal and power management features of the CPU (LEAF=0x06).

§Platforms

🟡 AMD ✅ Intel

Implementations§

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impl ThermalPowerInfo

pub fn dts_irq_threshold(&self) -> u8 ⓘ

Number of Interrupt Thresholds in Digital Thermal Sensor

§Platforms

❌ AMD (undefined/reserved) ✅ Intel

pub fn has_dts(&self) -> bool

Digital temperature sensor is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_turbo_boost(&self) -> bool

Intel Turbo Boost Technology Available (see description of IA32_MISC_ENABLE[38]).

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_arat(&self) -> bool

ARAT. APIC-Timer-always-running feature is supported if set.

§Platforms

✅ AMD ✅ Intel

pub fn has_pln(&self) -> bool

PLN. Power limit notification controls are supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_ecmd(&self) -> bool

ECMD. Clock modulation duty cycle extension is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_ptm(&self) -> bool

PTM. Package thermal management is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_hwp(&self) -> bool

HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_hwp_notification(&self) -> bool

HWP Notification. IA32_HWP_INTERRUPT MSR is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_hwp_activity_window(&self) -> bool

HWP Activity Window. IA32_HWP_REQUEST[bits 41:32] is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_hwp_energy_performance_preference(&self) -> bool

HWP Energy Performance Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_hwp_package_level_request(&self) -> bool

HWP Package Level Request. IA32_HWP_REQUEST_PKG MSR is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_hdc(&self) -> bool

HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_turbo_boost3(&self) -> bool

Intel® Turbo Boost Max Technology 3.0 available.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_hwp_capabilities(&self) -> bool

HWP Capabilities. Highest Performance change is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_hwp_peci_override(&self) -> bool

HWP PECI override is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_flexible_hwp(&self) -> bool

Flexible HWP is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_hwp_fast_access_mode(&self) -> bool

Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_ignore_idle_processor_hwp_request(&self) -> bool

Ignoring Idle Logical Processor HWP request is supported if set.

§Platforms

❌ AMD (reserved) ✅ Intel

pub fn has_hw_coord_feedback(&self) -> bool

Hardware Coordination Feedback Capability

Presence of IA32_MPERF and IA32_APERF.

The capability to provide a measure of delivered processor performance (since last reset of the counters), as a percentage of expected processor performance at frequency specified in CPUID Brand String Bits 02 - 01

§Platforms

✅ AMD ✅ Intel

pub fn has_energy_bias_pref(&self) -> bool

The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H)

§Platforms

❌ AMD (reserved) ✅ Intel

Trait Implementations§

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impl Debug for ThermalPowerInfo

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fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error> ⓘ

Formats the value using the given formatter. Read more

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