Struct ExtendedProcessorFeatureIdentifiers

pub struct ExtendedProcessorFeatureIdentifiers { /* private fields */ }

Available on crate feature dep_raw_cpuid only.

Extended Processor and Processor Feature Identifiers (LEAF=0x8000_0001)

Platforms

✅ AMD 🟡 Intel

Implementations

impl ExtendedProcessorFeatureIdentifiers

pub fn extended_signature(&self) -> u32

Extended Processor Signature.

AMD

The value returned is the same as the value returned in EAX for LEAF=0x0000_0001 (use CpuId.get_feature_info instead)

Intel

Vague mention of “Extended Processor Signature”, not clear what it’s supposed to represent.

Platforms

✅ AMD ✅ Intel

pub fn pkg_type(&self) -> u32

Returns package type on AMD.

Package type. If (Family[7:0] >= 10h), this field is valid. If (Family[7:0]<10h), this field is reserved

Platforms

✅ AMD ❌ Intel (reserved)

pub fn brand_id(&self) -> u32

Returns brand ID on AMD.

This field, in conjunction with CPUID LEAF=0x0000_0001_EBX[8BitBrandId], and used by firmware to generate the processor name string.

Platforms

✅ AMD ❌ Intel (reserved)

pub fn has_lahf_sahf(&self) -> bool

Is LAHF/SAHF available in 64-bit mode?

Platforms

✅ AMD ✅ Intel

pub fn has_cmp_legacy(&self) -> bool

Check support legacy cmp.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_svm(&self) -> bool

Secure virtual machine supported.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_ext_apic_space(&self) -> bool

Extended APIC space.

This bit indicates the presence of extended APIC register space starting at offset 400h from the “APIC Base Address Register,” as specified in the BKDG.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_alt_mov_cr8(&self) -> bool

LOCK MOV CR0 means MOV CR8. See “MOV(CRn)” in APM3.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_lzcnt(&self) -> bool

Is LZCNT available?

AMD

It’s called ABM (Advanced bit manipulation) on AMD and also adds support for some other instructions.

Platforms

✅ AMD ✅ Intel

pub fn has_sse4a(&self) -> bool

XTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support.

See “EXTRQ”, “INSERTQ”,“MOVNTSS”, and “MOVNTSD” in APM4.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_misaligned_sse_mode(&self) -> bool

Misaligned SSE mode. See “Misaligned Access Support Added for SSE Instructions” in APM1.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_prefetchw(&self) -> bool

Is PREFETCHW available?

AMD

PREFETCH and PREFETCHW instruction support.

Platforms

✅ AMD ✅ Intel

pub fn has_osvw(&self) -> bool

Indicates OS-visible workaround support

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_ibs(&self) -> bool

Instruction based sampling.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_xop(&self) -> bool

Extended operation support.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_skinit(&self) -> bool

SKINIT and STGI are supported.

Indicates support for SKINIT and STGI, independent of the value of MSRC000_0080[SVME].

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_wdt(&self) -> bool

Watchdog timer support.

Indicates support for MSRC001_0074.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_lwp(&self) -> bool

Lightweight profiling support

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_fma4(&self) -> bool

Four-operand FMA instruction support.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_tbm(&self) -> bool

Trailing bit manipulation instruction support.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_topology_extensions(&self) -> bool

Topology extensions support.

Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_perf_cntr_extensions(&self) -> bool

Processor performance counter extensions support.

Indicates support for MSRC001_020[A,8,6,4,2,0] and MSRC001_020[B,9,7,5,3,1].

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_nb_perf_cntr_extensions(&self) -> bool

NB performance counter extensions support.

Indicates support for MSRC001_024[6,4,2,0] and MSRC001_024[7,5,3,1].

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_data_access_bkpt_extension(&self) -> bool

Data access breakpoint extension.

Indicates support for MSRC001_1027 and MSRC001_101[B:9].

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_perf_tsc(&self) -> bool

Performance time-stamp counter.

Indicates support for MSRC001_0280 [Performance Time Stamp Counter].

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_perf_cntr_llc_extensions(&self) -> bool

Support for L3 performance counter extension.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_monitorx_mwaitx(&self) -> bool

Support for MWAITX and MONITORX instructions.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_addr_mask_extension(&self) -> bool

Breakpoint Addressing masking extended to bit 31.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_syscall_sysret(&self) -> bool

Are fast system calls available.

Platforms

✅ AMD ✅ Intel

pub fn has_execute_disable(&self) -> bool

Is there support for execute disable bit.

Platforms

✅ AMD ✅ Intel

pub fn has_mmx_extensions(&self) -> bool

AMD extensions to MMX instructions.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_fast_fxsave_fxstor(&self) -> bool

FXSAVE and FXRSTOR instruction optimizations.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_1gib_pages(&self) -> bool

Is there support for 1GiB pages.

Platforms

✅ AMD ✅ Intel

pub fn has_rdtscp(&self) -> bool

Check support for rdtscp instruction.

Platforms

✅ AMD ✅ Intel

pub fn has_64bit_mode(&self) -> bool

Check support for 64-bit mode.

Platforms

✅ AMD ✅ Intel

pub fn has_amd_3dnow_extensions(&self) -> bool

3DNow AMD extensions.

Platform

✅ AMD ❌ Intel (will return false)

pub fn has_3dnow(&self) -> bool

3DNow extensions.

Platform

✅ AMD ❌ Intel (will return false)

Trait Implementations

impl Debug for ExtendedProcessorFeatureIdentifiers

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.