Struct FeatureInfo
pub struct FeatureInfo { /* private fields */ }dep_raw_cpuid only.Expand description
Implementations§
§impl FeatureInfo
impl FeatureInfo
pub fn extended_family_id(&self) -> u8 ⓘ
pub fn extended_family_id(&self) -> u8 ⓘ
Version Information: Extended Family
pub fn extended_model_id(&self) -> u8 ⓘ
pub fn extended_model_id(&self) -> u8 ⓘ
Version Information: Extended Model
pub fn base_family_id(&self) -> u8 ⓘ
pub fn base_family_id(&self) -> u8 ⓘ
Version Information: Family
pub fn base_model_id(&self) -> u8 ⓘ
pub fn base_model_id(&self) -> u8 ⓘ
Version Information: Model
pub fn family_id(&self) -> u8 ⓘ
pub fn model_id(&self) -> u8 ⓘ
pub fn stepping_id(&self) -> u8 ⓘ
pub fn stepping_id(&self) -> u8 ⓘ
Version Information: Stepping ID
pub fn brand_index(&self) -> u8 ⓘ
pub fn brand_index(&self) -> u8 ⓘ
Brand Index
pub fn cflush_cache_line_size(&self) -> u8 ⓘ
pub fn cflush_cache_line_size(&self) -> u8 ⓘ
CLFLUSH line size (Value ∗ 8 = cache line size in bytes)
pub fn initial_local_apic_id(&self) -> u8 ⓘ
pub fn initial_local_apic_id(&self) -> u8 ⓘ
Initial APIC ID
pub fn max_logical_processor_ids(&self) -> u8 ⓘ
pub fn max_logical_processor_ids(&self) -> u8 ⓘ
Maximum number of addressable IDs for logical processors in this physical package.
pub fn has_sse3(&self) -> bool
pub fn has_sse3(&self) -> bool
Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this technology.
pub fn has_pclmulqdq(&self) -> bool
pub fn has_pclmulqdq(&self) -> bool
PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ instruction
pub fn has_ds_area(&self) -> bool
pub fn has_ds_area(&self) -> bool
64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout
pub fn has_monitor_mwait(&self) -> bool
pub fn has_monitor_mwait(&self) -> bool
MONITOR/MWAIT. A value of 1 indicates the processor supports this feature.
pub fn has_cpl(&self) -> bool
pub fn has_cpl(&self) -> bool
CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the Debug Store feature to allow for branch message storage qualified by CPL.
pub fn has_vmx(&self) -> bool
pub fn has_vmx(&self) -> bool
Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology.
pub fn has_smx(&self) -> bool
pub fn has_smx(&self) -> bool
Safer Mode Extensions. A value of 1 indicates that the processor supports this technology. See Chapter 5, Safer Mode Extensions Reference.
pub fn has_eist(&self) -> bool
pub fn has_eist(&self) -> bool
Enhanced Intel SpeedStep® technology. A value of 1 indicates that the processor supports this technology.
pub fn has_tm2(&self) -> bool
pub fn has_tm2(&self) -> bool
Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology.
pub fn has_ssse3(&self) -> bool
pub fn has_ssse3(&self) -> bool
A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction extensions are not present in the processor
pub fn has_cnxtid(&self) -> bool
pub fn has_cnxtid(&self) -> bool
L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode or shared mode. A value of 0 indicates this feature is not supported. See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.
pub fn has_fma(&self) -> bool
pub fn has_fma(&self) -> bool
A value of 1 indicates the processor supports FMA extensions using YMM state.
pub fn has_cmpxchg16b(&self) -> bool
pub fn has_cmpxchg16b(&self) -> bool
CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the CMPXCHG8B/CMPXCHG16B Compare and Exchange Bytes section. 14
pub fn has_pdcm(&self) -> bool
pub fn has_pdcm(&self) -> bool
Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance and debug feature indication MSR IA32_PERF_CAPABILITIES.
pub fn has_pcid(&self) -> bool
pub fn has_pcid(&self) -> bool
Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and the software may set CR4.PCIDE to 1.
pub fn has_dca(&self) -> bool
pub fn has_dca(&self) -> bool
A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped device.
pub fn has_x2apic(&self) -> bool
pub fn has_x2apic(&self) -> bool
A value of 1 indicates that the processor supports x2APIC feature.
pub fn has_movbe(&self) -> bool
pub fn has_movbe(&self) -> bool
A value of 1 indicates that the processor supports MOVBE instruction.
pub fn has_popcnt(&self) -> bool
pub fn has_popcnt(&self) -> bool
A value of 1 indicates that the processor supports the POPCNT instruction.
pub fn has_tsc_deadline(&self) -> bool
pub fn has_tsc_deadline(&self) -> bool
A value of 1 indicates that the processors local APIC timer supports one-shot operation using a TSC deadline value.
pub fn has_aesni(&self) -> bool
pub fn has_aesni(&self) -> bool
A value of 1 indicates that the processor supports the AESNI instruction extensions.
pub fn has_xsave(&self) -> bool
pub fn has_xsave(&self) -> bool
A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV instructions, and XCR0.
pub fn has_oxsave(&self) -> bool
pub fn has_oxsave(&self) -> bool
A value of 1 indicates that the OS has enabled XSETBV/XGETBV instructions to access XCR0, and support for processor extended state management using XSAVE/XRSTOR.
pub fn has_avx(&self) -> bool
pub fn has_avx(&self) -> bool
A value of 1 indicates the processor supports the AVX instruction extensions.
pub fn has_f16c(&self) -> bool
pub fn has_f16c(&self) -> bool
A value of 1 indicates that processor supports 16-bit floating-point conversion instructions.
pub fn has_rdrand(&self) -> bool
pub fn has_rdrand(&self) -> bool
A value of 1 indicates that processor supports RDRAND instruction.
pub fn has_hypervisor(&self) -> bool
pub fn has_hypervisor(&self) -> bool
A value of 1 indicates the indicates the presence of a hypervisor.
pub fn has_vme(&self) -> bool
pub fn has_vme(&self) -> bool
Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.
pub fn has_de(&self) -> bool
pub fn has_de(&self) -> bool
Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional trapping of accesses to DR4 and DR5.
pub fn has_pse(&self) -> bool
pub fn has_pse(&self) -> bool
Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs.
pub fn has_tsc(&self) -> bool
pub fn has_tsc(&self) -> bool
Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege.
pub fn has_msr(&self) -> bool
pub fn has_msr(&self) -> bool
Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are supported. Some of the MSRs are implementation dependent.
pub fn has_pae(&self) -> bool
pub fn has_pae(&self) -> bool
Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of 4 Mbyte pages if PAE bit is 1.
pub fn has_mce(&self) -> bool
pub fn has_mce(&self) -> bool
Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the feature. This feature does not define the model-specific implementations of machine-check error logging, reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor version to do model specific processing of the exception, or test for the presence of the Machine Check feature.
pub fn has_cmpxchg8b(&self) -> bool
pub fn has_cmpxchg8b(&self) -> bool
CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly locked and atomic).
pub fn has_apic(&self) -> bool
pub fn has_apic(&self) -> bool
APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some processors permit the APIC to be relocated).
pub fn has_sysenter_sysexit(&self) -> bool
pub fn has_sysenter_sysexit(&self) -> bool
SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported.
pub fn has_mtrr(&self) -> bool
pub fn has_mtrr(&self) -> bool
Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are supported.
pub fn has_pge(&self) -> bool
pub fn has_pge(&self) -> bool
Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.
pub fn has_mca(&self) -> bool
pub fn has_mca(&self) -> bool
Machine Check Architecture. A value of 1 indicates the Machine Check Architecture of reporting machine errors is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported.
pub fn has_cmov(&self) -> bool
pub fn has_cmov(&self) -> bool
Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported
pub fn has_pat(&self) -> bool
pub fn has_pat(&self) -> bool
Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear address on a 4KB granularity.
pub fn has_pse36(&self) -> bool
pub fn has_pse36(&self) -> bool
36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with 32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
pub fn has_psn(&self) -> bool
pub fn has_psn(&self) -> bool
Processor Serial Number. The processor supports the 96-bit processor identification number feature and the feature is enabled.
pub fn has_clflush(&self) -> bool
pub fn has_clflush(&self) -> bool
CLFLUSH Instruction. CLFLUSH Instruction is supported.
pub fn has_ds(&self) -> bool
pub fn has_ds(&self) -> bool
Debug Store. The processor supports the ability to write debug information into a memory resident buffer. This feature is used by the branch trace store (BTS) and processor event-based sampling (PEBS) facilities (see Chapter 23, Introduction to Virtual-Machine Extensions, in the Intel® 64 and IA-32 Architectures Software Developers Manual, Volume 3C).
pub fn has_acpi(&self) -> bool
pub fn has_acpi(&self) -> bool
Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control.
pub fn has_fxsave_fxstor(&self) -> bool
pub fn has_fxsave_fxstor(&self) -> bool
FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.
pub fn has_ss(&self) -> bool
pub fn has_ss(&self) -> bool
Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus.
pub fn has_htt(&self) -> bool
pub fn has_htt(&self) -> bool
Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is valid for the package.
pub fn has_tm(&self) -> bool
pub fn has_tm(&self) -> bool
Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).
pub fn has_pbe(&self) -> bool
pub fn has_pbe(&self) -> bool
Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
Trait Implementations§
Auto Trait Implementations§
impl Freeze for FeatureInfo
impl RefUnwindSafe for FeatureInfo
impl Send for FeatureInfo
impl Sync for FeatureInfo
impl Unpin for FeatureInfo
impl UnwindSafe for FeatureInfo
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