#[non_exhaustive]pub enum AtomicOrdering {
Relaxed,
Release,
Acquire,
AcqRel,
SeqCst,
}
Expand description
core
Atomic memory ordering.
Re-exported from core
::sync::atomic::
Ordering
→AtomicOrdering
.
Atomic memory orderings
Memory orderings specify the way atomic operations synchronize memory.
In its weakest Ordering::Relaxed
, only the memory directly touched by the
operation is synchronized. On the other hand, a store-load pair of Ordering::SeqCst
operations synchronize other memory while additionally preserving a total order of such
operations across all threads.
Rust’s memory orderings are the same as those of C++20.
For more information see the nomicon.
Variants (Non-exhaustive)§
This enum is marked as non-exhaustive
Relaxed
No ordering constraints, only atomic operations.
Corresponds to memory_order_relaxed
in C++20.
Release
When coupled with a store, all previous operations become ordered
before any load of this value with Acquire
(or stronger) ordering.
In particular, all previous writes become visible to all threads
that perform an Acquire
(or stronger) load of this value.
Notice that using this ordering for an operation that combines loads
and stores leads to a Relaxed
load operation!
This ordering is only applicable for operations that can perform a store.
Corresponds to memory_order_release
in C++20.
Acquire
When coupled with a load, if the loaded value was written by a store operation with
Release
(or stronger) ordering, then all subsequent operations
become ordered after that store. In particular, all subsequent loads will see data
written before the store.
Notice that using this ordering for an operation that combines loads
and stores leads to a Relaxed
store operation!
This ordering is only applicable for operations that can perform a load.
Corresponds to memory_order_acquire
in C++20.
AcqRel
Has the effects of both Acquire
and Release
together:
For loads it uses Acquire
ordering. For stores it uses the Release
ordering.
Notice that in the case of compare_and_swap
, it is possible that the operation ends up
not performing any store and hence it has just Acquire
ordering. However,
AcqRel
will never perform Relaxed
accesses.
This ordering is only applicable for operations that combine both loads and stores.
Corresponds to memory_order_acq_rel
in C++20.
SeqCst
Like Acquire
/Release
/AcqRel
(for load, store, and load-with-store
operations, respectively) with the additional guarantee that all threads see all
sequentially consistent operations in the same order.
Corresponds to memory_order_seq_cst
in C++20.
Trait Implementations§
Source§impl BitSized<8> for AtomicOrdering
impl BitSized<8> for AtomicOrdering
Source§const BIT_SIZE: usize = _
const BIT_SIZE: usize = _
Source§const MIN_BYTE_SIZE: usize = _
const MIN_BYTE_SIZE: usize = _
§impl CompareAndSetOrdering for Ordering
impl CompareAndSetOrdering for Ordering
impl Copy for Ordering
impl Eq for Ordering
impl StructuralPartialEq for Ordering
Auto Trait Implementations§
impl Freeze for Ordering
impl RefUnwindSafe for Ordering
impl Send for Ordering
impl Sync for Ordering
impl Unpin for Ordering
impl UnwindSafe for Ordering
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